LDMOS with double LDD and trenched drain

ABSTRACT

A LDMOS with double LDD and trenched drain is disclosed. According to some preferred embodiment of the present invention, the structure contains a double LDD region, including a high energy implantation to form lightly doped region and a low energy implantation thereon to provide a low resistance path for current flow without degrading breakdown voltage. At the same time, a P+ junction made by source mask is provided underneath source region to avoid latch-up effect from happening.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to the cell structure and fabricationprocess of power semiconductor devices. More particularly, thisinvention relates to a novel and improved cell structure and improvedprocess for fabricating a LDMOS (Laterally Diffused MOS transistors)with double LDD (Lightly Doped Drain) and trenched drain structure toprovide a low resistance path for the current with enhanced FOMcharacteristic.

2. The Prior Arts

In U.S. Pat. No. 7,282,765, a LDMOS transistor cell with substratehaving a first N semiconductor doping type of prior art was disclosed,as shown in FIG. 1. The transistor cell structure comprises: a highly N+doped substrate 100 onto which formed a lightly doped epitaxial layer102 having dopants of N or P dopant type; a body region 104 having Ptype dopants within which implanted an N+ source region 106; a LDDregion 108 formed into epitaxial layer 102 while adjacent to the topsurface of said epitaxial layer; a vertical drain contact region 110where current flows through; a deep trench region 112 for the formationof vertical drain contact region 110 while its open; conductive gateincluding a doped polysilicon layer 114 and an upper silicide layer 115formed over a gate dielectric 113; an insulating layer 116 covering thesource region 106, the conductive gate sidewalls and its upper surface,and the LDD region 108. The illustrated structure further comprises ashallow trench region 118 by which body region 104 and source region 106are connected to source metal 119, while a body contact doping region117 having a dopant concentration P++ greater than the concentration ofbody region is introduced to reduce the resistance between body regionand source metal.

As analyzed in prior art, the LDD region 108 increases thedrain-to-source breakdown voltage (BV) of the LDMOS due to its lowerdoping concentration. However, the low concentration of drain region cannot provide a low resistance path for current flow, that means the onresistance between drain and source (Rdson) is large due to low dopingconcentration in drain region, which will lead to a large conductionloss. Therefore, it is necessary to make a compromise between breakdownvoltage and Rdson to optimize the device performance.

Another disadvantage of the prior art is that, there is a high parasiticresistance R_(L) 109 between surface of the LDD region 108 and N+ region110 connected to bottom of LDD region 108 due to the lower dopingconcentration, causing high Rdson between drain and source.

Another disadvantage of the prior is that, a parasitic bipolar N+PN inthe prior art is easily triggered on due to existence of high baseresistance R_(B) 111 underneath source region 106, resulting in devicedestroy.

Accordingly, it would be desirable to provide a new LDMOS cell structurewith low on-resistance between the source region and drain region whilesustaining a high breakdown voltage without triggering on the parasiticbipolar.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide new andimproved LDMOS cell and manufacture process to reduce the on resistanceand increase breakdown voltage, while remaining a lower fabricatingcost.

One aspect of the present invention is that, as shown in FIG. 2, andFIGS. 4 to 8, after the LDD-N1 implantation for the formation of driftdrain region with a higher energy, another low energy LDD implantationwith a higher doping concentration is introduced above said LDD-N1region with the same mask to form LDD-N2. By employing the double LDDstructure, the low energy implantation provides a low on-resistance pathfor the current flow, while the high energy implantation forms a lightlydoped region to sustain a high breakdown voltage. FIG. 3 shows dopingprofile of the double LDD in comparison with the single LDD in priorart. The simulation result of Rdson when Vg=10V is shown in Table 1, itsvalue is reduced to about 41% comparing to the prior art in FIG. 1.Besides this, when considering the FOM (Figure of Merit) value which isdefined by Rdson times Qg, it also can be seen from Table 1 that, thestructure of the present invention is well optimized by reducing the FOMto 61% of prior art, thus a successfully compromise is achieved byemploying the present invention.

TABLE 1 Simulated Parameters when Vgs = 10 V FOM BV Rdson Qgd Qg(Rdson * Qg) Device (V) (mohm · mm²) (nC/mm²) (nC/mm²) (mohm · nC)Single 20 10 0.5 2.2 22 LDD Double 25 5.9 1.1 1.9 11.2 LDD

Another aspect of the present invention is that, as shown in FIG. 2, andFIGS. 3 to 8, before the source implantation, a step of P+ implantationfor the formation of avalanche improved region is carried out with aconcentration from 1E18 to 5E19 atoms/cm³ to form a P+ area underneathsource region for reducing the base resistance in the parasitic bipolar.

Another aspect of the present invention is that, in some preferredembodiments, as shown in FIGS. 4, 6, and 8, Vth (threshold voltage) ofthe LDMOS is adjusted by Ion Implantation in channel region with dopantopposite to body region, e.g., N type dopant. The Rdson can be reducedfurther without having punch-through issue.

Another aspect of the present invention is that, in some preferredembodiments, as shown in FIG. 5 and FIG. 6, in order to reduce contactdimension, trench source-body contact structure which is same as theprior art, is employed to take place of traditional planar contact asused in FIG. 2 and FIG. 4.

Another aspect of the present invention is that, as shown in FIG. 7 andFIG. 8, the contact CD can be further shrunk with filling tungsten pluginto the source-body contact trench and metal step coverage is also thussignificantly improved.

Another aspect of the present invention is that, as no additional maskis required to implement the LDD-N2 implantation and P+ area duringfabricating process, the device has better performance of high BV andlow Rdson than the prior art without extra fabrication cost.

Briefly, in a preferred embodiment, as shown in FIG. 2, the presentinvention disclosed a LDMOS cell comprising: a substrate having a firstconductivity doping type, e.g., N doping type, with a resistivity ofless than 3 mohm-cm onto which a lightly doped epitaxial layer with asecond conductivity doping type is grown, e.g., P doping type; a bodyregion of P doped formed inside said epitaxial layer near the uppersurface, within which an N+ source region is formed above the P+avalanche improved region; LDD-N1 region implanted within said epitaxiallayer adjacent to said body region and separated from said source regionby channel region; LDD-N2 region implanted near the top surface ofLDD-N1 region to further reduce the path resistance for current flow; aconductive gate formed onto a first insulating layer over channel regionand partially covers source region, LDD-N1 and LDD-N2 region with alayer of silicide thereon; a first trench serving as drain contacttrench opened through said epitaxial layer adjacent to LDD region toenable the formation of drain contact region and filled with doped poly,Ti/TiN/W or Co/TiN/W plug; a highly N+ doped region surrounding sidewallof the drain contact trench and connecting the LDD-N1 and LDD-N2; asecond insulating layer covering the source region, the conductive gatesidewalls and its upper surface, and the LDD region; P++ body contactdoping region next to said source region near the top surface of bodyregion above P+ avalanche improved region to provide a low resistancecontact between front metal and body region; source metal formed oversaid second insulating layer to contact source region and said P++bodycontact doping region laterally.

Briefly, in another preferred embodiment, as shown in FIG. 4, thepresent invention disclosed a similar LDMOS cell to structure in FIG. 2except that, the channel region of cell structure in FIG. 4 was IonImplanted with dopant of opposite doping type to body region to adjustedVth to a lower value for Rdson reduction.

Briefly, in another preferred embodiment, as shown in FIG. 5, thepresent invention disclosed a similar LDMOS cell to structure in FIG. 2except that, a second trench serving as source-body contact trench isetched through said second insulating layer and said source region, andinto said the P+ avalanche improved region or through P+ avalancheimproved region into P body region. Accordingly, said P++ body contactdoping region area is formed around the bottom of said second trench toprovide a low resistance contact between body region and source metalfilled into said second trench.

Briefly, in another preferred embodiment, as shown in FIG. 6, thepresent invention disclosed a similar LDMOS cell to structure in FIG. 5except that, the channel region of cell structure in FIG. 6 was IonImplanted with dopant of opposite doping type to body region to adjustedVth to a lower value for Rdson reduction.

Briefly, in another preferred embodiment, as shown in FIGS. 7 and 8, thepresent invention disclosed a similar LDMOS cell to structures in FIGS.5 and 6, respectively. The devices further comprises the source-bodycontact trench padded with a barrier layer composed of Ti/TiN or Co/TiNand filled with tungsten contact plugs for contacting the body regionsand source regions. Each of these source contact trenches further areextended into body regions having a body contact doping region implantedbelow the contact trenches to reduce the contact resistance. The topsurface of the second insulation layer is covered with a metalresistance-reduction interlayer composed of Ti or Ti/TiN for reducingcontact resistance between the tungsten plug and source metal.

These and other objects and advantages of the present invention will nodoubt become obvious to those of ordinary skill in the art after havingread the following detailed description of the preferred embodiment,which is illustrated in the various drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by reading thefollowing detailed description of the preferred embodiments, withreference made to the accompanying drawings, wherein:

FIG. 1 is a side cross-sectional view of a LDMOS cell of prior art.

FIG. 2 is a side cross-sectional view of a preferred embodiment inaccordance with the present invention.

FIG. 3 is doping profile comparison between single LDD and double LDD.

FIG. 4 is a side cross-sectional view of another preferred embodiment inaccordance with the present invention.

FIG. 5 is a side cross-sectional view of another preferred embodiment inaccordance with the present invention.

FIG. 6 is a side cross-sectional view of another preferred embodiment inaccordance with the present invention.

FIG. 7 is a side cross-sectional view of another preferred embodiment inaccordance with the present invention.

FIG. 8 is a side cross-sectional view of another preferred embodiment inaccordance with the present invention.

FIGS. 9A to 9D are a serial of side cross sectional views for showingthe processing steps for fabricating LDMOS cell in FIG. 5.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Please refer to FIG. 2 for a preferred embodiment of the presentinvention. The shown LDMOS cell is formed on an N+ substrate 200 ontowhich grown a P− epitaxial layer 202 wherein P body region 204 isimplanted. Source region 206 is formed near the top surface of P bodyregion 204 with a P+ avalanche improved region 217 underneath using thesame source mask. Adjacent to LDD-N1 region 208 and LDD-N2 region 209which is implanted successively near the top surface of epitaxial layer,a first trench is etched through epitaxial layer and filled with dopedpoly, Ti/TiN/W or Co/TiN/W as drain contact metal plug 212. A highlydoped region 210 of N+ doping type is formed next to said drain contactunderneath LDD-N1 region to provide a low resistance path for currentflow. Above a first insulating layer, which serves as gate oxide layer213, conductive gate 214 is formed over channel region with a layer ofsilicide 215 thereon, partially overlaps source region 206, LDD-N1region 208 and LDD-N2 region 209. Source metal 219 is deposited on asecond insulating layer 216 and contact source region 206 and bodyregion 204 laterally through a P++ body contact doping region 218 whichreduces the resistance between body region and front source metal.

FIG. 4 shows another preferred embodiment of the present invention.Comparing to FIG. 2, the channel region 420 of the structure in FIG. 4is Ion Implanted with dopant of opposite doping type to body region toreduce the threshold voltage.

FIG. 5 shows another preferred embodiment of the present invention.Comparing to FIG. 2, the structure in FIG. 5 has a second trench etchedthrough said second insulating layer 516, said source region 506 andinto the P+ avalanche improved region 517 to serve as source-bodycontact trench. Around the bottom of said second trench, a P++ bodycontact doping region 518 is accordingly formed to reduce the resistancebetween body region 504 and front source metal 519.

FIG. 6 shows another preferred embodiment of the present invention.Comparing to FIG. 5, the channel region 620 of the structure in FIG. 6is Ion Implanted with dopant of opposite doping type to body region toreduce the threshold voltage.

FIGS. 7 and 8 show another preferred embodiments of the presentinvention. Comparing to FIGS. 5 and 6, the source-body contact trench isfilled with Tungsten plug padded with a barrier layer composed of Ti/TiNor Co/TiN. The top surface of the second insulation layer is coveredwith a metal resistance-reduction interlayer composed of Ti or Ti/TiNfor reducing contact resistance between the tungsten plug and the sourcemetal.

FIGS. 9A to 9D show a series of exemplary steps that are performed toform the inventive LDMOS of the present invention shown in FIG. 5. InFIG. 9A, a P− doped epitaxial layer 502 is grown on an N+ substrate 500,e.g., Arsenic doped substrate, then, a trench mask (not shown) isapplied, which is then conventionally exposed and patterned to leavemask portions. The patterned mask portions define the first trench 512′,which is dry silicon etched through mask to the interface betweensubstrate and epitaxial layer. Next, a sacrificial oxide (not shown) isgrown and then removed to eliminate the plasma damage may introducedduring trenches etching process. After the trench mask removal, an angleAs implantation is carried out above first trench 512′ with ±3 degreerespecting to top surface of epitaxial layer to form the N+ region 510adjacent to said first trench, as shown in FIG. 9B. Next, doped poly,Ti/TiN/W or Co/TiN/W plug is deposited into trench 512′ to form draincontact plug 512 and is then CMP (Chemical Mechanical Polishing) oretched back to expose the epitaxial layer. After that, P bodyimplantation is carried out above P body mask (not shown) to form bodyregion 504. Refer to FIG. 9C, a first insulating layer, doped poly andsilicide layer are deposited successively onto the top surface ofepitaxial layer and then etched back to form gate oxide 513 andconductivity gate 514 with silicide 515 thereon. Then, a high energy LDDArsenic or Phosphorus implantation with 150-300 KeV and 1E115E11 cm⁻³dose; and low energy LDD Arsenic or phosphorus implantation with 60˜100KeV and 1E12˜5E12 cm⁻³ dose are successively continued to form LDD-N1region 508 and LDD-N2 region 509 followed by a step of LDD annealprocess. Next, with the same source mask (not shown), Boron implantationis applied to form P+ avalanche improved region 517, followed by Arsenicimplantation for the formation of source region 506 and a step of sourceanneal. After that, in FIG. 9D, a second insulating layer 516 isdeposited along the whole surface of device onto which formed sourcecontact mask (not shown) for the etching of second trench by dry oxideetching through second insulating layer 516 and dry silicon etchingthrough source region 506 and into P+ avalanche improved region 517.Above the second trench, BF2 Ion Implantation is implemented to form theP++body contact doping region 518 around the bottom of said secondtrench. At last, source metal 519 is deposited filling the second trenchand covering the second insulating layer 516.

Although the present invention has been described in terms of thepresently preferred embodiments, it is to be understood that suchdisclosure is not to be interpreted as limiting. Various alternationsand modifications will no doubt become apparent to those skilled in theart after reading the above disclosure. Accordingly, it is intended thatthe appended claims be interpreted as covering all alternations andmodifications as fall within the true spirit and scope of the invention.

1. A LDMOS cell with double LDD and trenched drain comprising: asubstrate of a first type conductivity; an epitaxial layer of secondtype conductivity over said substrate, having a lower dopingconcentration than said substrate; a body region of said second typeconductivity within said epitaxial layer, having a higher dopingconcentration than said epitaxial layer; a source region of said firsttype conductivity formed near the top surface of said body region; anavalanche improved region of said second type conductivity underneathsaid source region inside said body region, having a higher dopingconcentration than said body region; a body contact doping region ofsaid second type conductivity adjacent to said source region above saidavalanche improved region, having a higher doping concentration thansaid avalanche improved region; a first LDD implantation region LDD-N1separated from said source region by channel region inside saidepitaxial layer; a second LDD implantation region LDD-N2 within LDD-N1region, formed by a lower energy and higher doping concentration thansaid LDD-N1 region; a drain contact trench etched through epitaxiallayer and into said substrate; a highly doped region of said firstconductivity type formed along sidewalls of the drain contact trench andconnect with said first LDD and second LDD implantation region; aconductive plug filled into said drain contact trench to serve as draincontact plug; a first insulating layer acting as gate dielectric; aconductive gate formed on said first insulating layer over said channelregion and partially overlapping said source region and said LDD regionwith a layer of silicide thereon; a second insulating layer coveringsaid source region, said conductive gate sidewalls and its uppersurface, and said LDD region and said drain contact plug; a source metallocated onto said second insulating layer and contacting said sourceregion and said body contact doping region laterally.
 2. The LDMOS ofclaim 1, heavily doped poly served as conductive plug is filled intosaid drain contact trench.
 3. The LDMOSE of claim 1, Ti/TiN/W orCo/TiN/W served as conductive plug is filled into said drain contacttrench.
 4. The LDMOS of claim 1, the conductive gate is heavily dopedpoly.
 5. The LDMOSE of claim 1, the first LDD has Arsenic or Phosphorusimplantation with energy rang from 150˜300 KeV and dose rang from1E11˜5E11 cm⁻³.
 6. The LDMOSE of claim 1, the second LDD has Arsenic orPhosphorus implantation with energy rang from 60˜100 KeV and dose rangfrom 1E12˜5E12 cm⁻³.
 7. The LDMOS of claim 1, wherein said channelregion is not ion implanted with dopant opposite to body region toadjust the threshold voltage.
 8. The LDMOS of claim 1, wherein saidchannel region is ion Implanted with dopant opposite to body region toadjust the threshold voltage.
 9. A LDMOS cell with double LDD andtrenched drain comprising: a substrate of a first type conductivity; anepitaxial layer of second type conductivity over said substrate having alower doping concentration than said substrate; a body region of saidsecond type conductivity within said epitaxial layer, having a higherdoping concentration than said epitaxial layer; a source region of saidfirst type conductivity formed near the top surface of said body region;an avalanche improved region of said second type conductivity underneathsaid source region inside said body region, having a higher dopingconcentration than said body region; a body contact doping region ofsaid second type conductivity adjacent to said source region above saidavalanche improved region, having a higher doping concentration thansaid avalanche improved region; a first LDD implantation region LDD-N1separated from said source region by channel region inside saidepitaxial layer; a second LDD implantation region LDD-N2 within LDD-N1region, formed by a lower energy and higher doping concentration thansaid LDD-N1 region; a first drain contact trench etched throughepitaxial layer and into said substrate; a highly doped region of saidfirst conductivity type formed along sidewalls of the drain contacttrench and connect with said first LDD and second LDD implantationregion; a conductive plug filled into said drain contact trench to serveas drain contact plug; a first insulating layer acting as gatedielectric; a conductive gate formed on said first insulating layer oversaid channel region and partially overlapping said source region andsaid LDD region with a layer of silicide thereon; a second insulatinglayer covering said source region, said conductive gate sidewalls andits upper surface, and said LDD region and said drain contact plug; asource-body contact trench etched through said second insulating layer,said source region and into said avalanche improved region or throughsaid avalanche improved region and into said body region as source-bodycontact trench; a body contact doping region around the bottom of saidsecond trench; a source metal located onto said second insulating layerand filling into said second trench to contact said source region andsaid body region.
 10. The LDMOS of claim 9, heavily doped poly served asconductive plug is filled into said drain contact trench.
 11. The LDMOSEof claim 9, Ti/TiN/W or Co/TiN/W served as conductive plug is filledinto said drain contact trench.
 12. The LDMOS of claim 9, the conductivegate is heavily doped poly.
 13. The LDMOS of claim 9, the first LDD hasArsenic or Phosphorus implantation with energy rang from 150˜300 KeV anddose rang from 1E11˜5E11 cm⁻³.
 14. The LDMOSE of claim 9, the second LDDhas Arsenic or Phosphorus implantation with energy rang from 60-100 KeVand dose rang from 1E12˜5E12 cm⁻³.
 15. The LDMOS of claim 9, whereinsaid channel region is not ion implanted with dopant opposite to bodyregion to adjust the threshold voltage.
 16. The LDMOS of claim 9,wherein said channel region is Ion Implanted with dopant opposite tobody region to adjust the threshold voltage.
 17. A LDMOS cell withdouble LDD and trenched drain comprising: a substrate of a first typeconductivity; an epitaxial layer of second type conductivity over saidsubstrate having a lower doping concentration than said substrate; abody region of said second type conductivity within said epitaxiallayer, having a higher doping concentration than said epitaxial layer; asource region of said first type conductivity formed near the topsurface of said body region; an avalanche improved region of said secondtype conductivity underneath said source region inside said body region,having a higher doping concentration than said body region; a bodycontact doping region of said second type conductivity adjacent to saidsource region above said avalanche improved region, having a higherdoping concentration than said avalanche improved; a first LDDimplantation region LDD-N1 separated from said source region by channelregion inside said epitaxial layer; a second LDD implantation regionLDD-N2 within LDD-N1 region, formed by a lower energy and higher dopingconcentration than said LDD-N1 region; a first drain contact trenchetched through epitaxial layer and into N+ substrate; a highly dopedregion of said first conductivity type formed along sidewalls of thedrain contact trench and connect with said first LDD and second LDDimplantation region; a conductive plug filled into said drain contacttrench to serve as drain contact plug; a first insulating layer actingas gate dielectric; a conductive gate formed on said first insulatinglayer over said channel region and partially overlapping said sourceregion and said LDD region with a layer of silicide thereon; a secondinsulating layer covering said source region, said conductive gatesidewalls and its upper surface, and said LDD region and said draincontact plug; a source-body contact trench etched through said secondinsulating layer, said source region and into said avalanche improvedregion or through said avalanche improved region and into said bodyregion as source-body contact trench; a body contact doping regionaround the bottom of said second trench; a barrier metal layer andtungsten plug is filled into said second trench; a source metal over ametal resistance reduction interlayer, located onto said secondinsulating layer and said tungsten plug.
 18. The LDMOS of claim 17,wherein said barrier metal is Ti/TiN or Co/TiN.
 19. The LDMOS of claim17, wherein said metal resistance reduction interlayer is Ti or Ti/TiN.20. The LDMOS of claim 17, heavily doped poly served as conductive plugis filled into said drain contact trench.
 21. The LDMOSE of claim 17,Ti/TiN/W or Co/TiN/W served as conductive plug is filled into said draincontact trench.
 22. A method for manufacturing a LDMOS cell with doubleLDD and trenched drain comprising the steps of: growing an epitaxiallayer upon a heavily first type conductivity doped substrate, e.g., Nsubstrate, wherein said epitaxial layer is doped with a second typedopant, e.g., P dopant; forming a first trench mask with open and closedareas on the surface of said epitaxial layer; removing semiconductormaterial from exposed areas of said trench mask to form first trench asdrain contact trench; growing a sacrificial oxide layer onto the surfaceof said first trenches to remove the plasma damage introduced duringopening said first trench; removing said sacrificial oxide and saidtrench mask; implanting said first trench with N type dopant by angleimplantation of ±3 degree respecting to the top surface of saidepitaxial layer; depositing doped poly onto said epitaxial layer andinto said first trench; etching back or CMP said doped poly from thesurface of said epitaxial layer and leaving doped poly into said firsttrench to serve as drain contact plug; forming a body mask andimplanting with P type dopant; removing said body mask and depositing afirst insulating layer onto the top surface of said epitaxial layer;depositing doped poly and silicide layer successively onto said firstinsulating layer; etching back said silicide and said doped poly throughgate mask to form conductive gate; implanting semiconductor device withN type dopant under 300 KeV to form LDD-N1 region; implantingsemiconductor device with N type dopant heavier than LDD-N1 under 100KeV to form LDD-N2 region; forming a source mask and implanting with Ptype dopant to form P+ avalanche improved region; implanting said sourcemask with N type dopant to form source region above said P+ avalancheimproved region; removing said source mask and depositing a secondinsulating layer onto whole surface and applying a second trench mask;removing oxide material and semiconductor material from exposed areas ofsaid contact mask to form said second trench serving as source-bodycontact trench; implanting said source-body contact trench with BF2 ionto form P++ area around the bottom of said source-body contact trench;removing said contact mask and depositing metal material into saidsource-body contact trench and onto said second insulating layer.